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<div class="header">
  <div class="headertitle"><div class="title">nvic.h</div></div>
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<div class="fragment"><div class="line"><a id="l00001" name="l00001"></a><span class="lineno">    1</span><span class="comment">// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT</span></div>
<div class="line"><a id="l00002" name="l00002"></a><span class="lineno">    2</span> </div>
<div class="line"><a id="l00008" name="l00008"></a><span class="lineno">    8</span><span class="preprocessor">#ifndef _HARDWARE_STRUCTS_NVIC_H</span></div>
<div class="line"><a id="l00009" name="l00009"></a><span class="lineno">    9</span><span class="preprocessor">#define _HARDWARE_STRUCTS_NVIC_H</span></div>
<div class="line"><a id="l00010" name="l00010"></a><span class="lineno">   10</span> </div>
<div class="line"><a id="l00011" name="l00011"></a><span class="lineno">   11</span><span class="preprocessor">#include &quot;<a class="code" href="address__mapped_8h.html">hardware/address_mapped.h</a>&quot;</span></div>
<div class="line"><a id="l00012" name="l00012"></a><span class="lineno">   12</span><span class="preprocessor">#include &quot;hardware/regs/m33.h&quot;</span></div>
<div class="line"><a id="l00013" name="l00013"></a><span class="lineno">   13</span> </div>
<div class="line"><a id="l00014" name="l00014"></a><span class="lineno">   14</span><span class="comment">// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33</span></div>
<div class="line"><a id="l00015" name="l00015"></a><span class="lineno">   15</span><span class="comment">//</span></div>
<div class="line"><a id="l00016" name="l00016"></a><span class="lineno">   16</span><span class="comment">// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the &quot;Go to Definition&quot; feature)</span></div>
<div class="line"><a id="l00017" name="l00017"></a><span class="lineno">   17</span><span class="comment">// _REG_(x) will link to the corresponding register in hardware/regs/m33.h.</span></div>
<div class="line"><a id="l00018" name="l00018"></a><span class="lineno">   18</span><span class="comment">//</span></div>
<div class="line"><a id="l00019" name="l00019"></a><span class="lineno">   19</span><span class="comment">// Bit-field descriptions are of the form:</span></div>
<div class="line"><a id="l00020" name="l00020"></a><span class="lineno">   20</span><span class="comment">// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION</span></div>
<div class="line"><a id="l00021" name="l00021"></a><span class="lineno">   21</span> </div>
<div class="line"><a id="l00022" name="l00022"></a><span class="lineno">   22</span><span class="preprocessor">#if defined(__riscv) &amp;&amp; PICO_FORBID_ARM_HEADERS_ON_RISCV</span></div>
<div class="line"><a id="l00023" name="l00023"></a><span class="lineno">   23</span><span class="preprocessor">#error &quot;Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1&quot;</span></div>
<div class="line"><a id="l00024" name="l00024"></a><span class="lineno">   24</span><span class="preprocessor">#endif</span></div>
<div class="line"><a id="l00025" name="l00025"></a><span class="lineno">   25</span> </div>
<div class="line"><a id="l00026" name="l00026"></a><span class="lineno"><a class="line" href="structnvic__hw__t.html">   26</a></span><span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
<div class="line"><a id="l00027" name="l00027"></a><span class="lineno">   27</span>    <span class="comment">// (Description copied from array index 0 register M33_NVIC_ISER0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00028" name="l00028"></a><span class="lineno">   28</span>    _REG_(M33_NVIC_ISER0_OFFSET) <span class="comment">// M33_NVIC_ISER0</span></div>
<div class="line"><a id="l00029" name="l00029"></a><span class="lineno">   29</span>    <span class="comment">// Enables or reads the enabled state of each group of 32 interrupts</span></div>
<div class="line"><a id="l00030" name="l00030"></a><span class="lineno">   30</span>    <span class="comment">// 0xffffffff [31:0]  SETENA       (0x00000000) For SETENA[m] in NVIC_ISER*n, indicates whether...</span></div>
<div class="line"><a id="l00031" name="l00031"></a><span class="lineno">   31</span>    io_rw_32 iser[2];</div>
<div class="line"><a id="l00032" name="l00032"></a><span class="lineno">   32</span> </div>
<div class="line"><a id="l00033" name="l00033"></a><span class="lineno">   33</span>    uint32_t _pad0[30];</div>
<div class="line"><a id="l00034" name="l00034"></a><span class="lineno">   34</span> </div>
<div class="line"><a id="l00035" name="l00035"></a><span class="lineno">   35</span>    <span class="comment">// (Description copied from array index 0 register M33_NVIC_ICER0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00036" name="l00036"></a><span class="lineno">   36</span>    _REG_(M33_NVIC_ICER0_OFFSET) <span class="comment">// M33_NVIC_ICER0</span></div>
<div class="line"><a id="l00037" name="l00037"></a><span class="lineno">   37</span>    <span class="comment">// Clears or reads the enabled state of each group of 32 interrupts</span></div>
<div class="line"><a id="l00038" name="l00038"></a><span class="lineno">   38</span>    <span class="comment">// 0xffffffff [31:0]  CLRENA       (0x00000000) For CLRENA[m] in NVIC_ICER*n, indicates whether...</span></div>
<div class="line"><a id="l00039" name="l00039"></a><span class="lineno">   39</span>    io_rw_32 icer[2];</div>
<div class="line"><a id="l00040" name="l00040"></a><span class="lineno">   40</span> </div>
<div class="line"><a id="l00041" name="l00041"></a><span class="lineno">   41</span>    uint32_t _pad1[30];</div>
<div class="line"><a id="l00042" name="l00042"></a><span class="lineno">   42</span> </div>
<div class="line"><a id="l00043" name="l00043"></a><span class="lineno">   43</span>    <span class="comment">// (Description copied from array index 0 register M33_NVIC_ISPR0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00044" name="l00044"></a><span class="lineno">   44</span>    _REG_(M33_NVIC_ISPR0_OFFSET) <span class="comment">// M33_NVIC_ISPR0</span></div>
<div class="line"><a id="l00045" name="l00045"></a><span class="lineno">   45</span>    <span class="comment">// Enables or reads the pending state of each group of 32 interrupts</span></div>
<div class="line"><a id="l00046" name="l00046"></a><span class="lineno">   46</span>    <span class="comment">// 0xffffffff [31:0]  SETPEND      (0x00000000) For SETPEND[m] in NVIC_ISPR*n, indicates whether...</span></div>
<div class="line"><a id="l00047" name="l00047"></a><span class="lineno">   47</span>    io_rw_32 ispr[2];</div>
<div class="line"><a id="l00048" name="l00048"></a><span class="lineno">   48</span> </div>
<div class="line"><a id="l00049" name="l00049"></a><span class="lineno">   49</span>    uint32_t _pad2[30];</div>
<div class="line"><a id="l00050" name="l00050"></a><span class="lineno">   50</span> </div>
<div class="line"><a id="l00051" name="l00051"></a><span class="lineno">   51</span>    <span class="comment">// (Description copied from array index 0 register M33_NVIC_ICPR0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00052" name="l00052"></a><span class="lineno">   52</span>    _REG_(M33_NVIC_ICPR0_OFFSET) <span class="comment">// M33_NVIC_ICPR0</span></div>
<div class="line"><a id="l00053" name="l00053"></a><span class="lineno">   53</span>    <span class="comment">// Clears or reads the pending state of each group of 32 interrupts</span></div>
<div class="line"><a id="l00054" name="l00054"></a><span class="lineno">   54</span>    <span class="comment">// 0xffffffff [31:0]  CLRPEND      (0x00000000) For CLRPEND[m] in NVIC_ICPR*n, indicates whether...</span></div>
<div class="line"><a id="l00055" name="l00055"></a><span class="lineno">   55</span>    io_rw_32 icpr[2];</div>
<div class="line"><a id="l00056" name="l00056"></a><span class="lineno">   56</span> </div>
<div class="line"><a id="l00057" name="l00057"></a><span class="lineno">   57</span>    uint32_t _pad3[30];</div>
<div class="line"><a id="l00058" name="l00058"></a><span class="lineno">   58</span> </div>
<div class="line"><a id="l00059" name="l00059"></a><span class="lineno">   59</span>    <span class="comment">// (Description copied from array index 0 register M33_NVIC_IABR0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00060" name="l00060"></a><span class="lineno">   60</span>    _REG_(M33_NVIC_IABR0_OFFSET) <span class="comment">// M33_NVIC_IABR0</span></div>
<div class="line"><a id="l00061" name="l00061"></a><span class="lineno">   61</span>    <span class="comment">// For each group of 32 interrupts, shows the active state of each interrupt</span></div>
<div class="line"><a id="l00062" name="l00062"></a><span class="lineno">   62</span>    <span class="comment">// 0xffffffff [31:0]  ACTIVE       (0x00000000) For ACTIVE[m] in NVIC_IABR*n, indicates the active state...</span></div>
<div class="line"><a id="l00063" name="l00063"></a><span class="lineno">   63</span>    io_rw_32 iabr[2];</div>
<div class="line"><a id="l00064" name="l00064"></a><span class="lineno">   64</span> </div>
<div class="line"><a id="l00065" name="l00065"></a><span class="lineno">   65</span>    uint32_t _pad4[30];</div>
<div class="line"><a id="l00066" name="l00066"></a><span class="lineno">   66</span> </div>
<div class="line"><a id="l00067" name="l00067"></a><span class="lineno">   67</span>    <span class="comment">// (Description copied from array index 0 register M33_NVIC_ITNS0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00068" name="l00068"></a><span class="lineno">   68</span>    _REG_(M33_NVIC_ITNS0_OFFSET) <span class="comment">// M33_NVIC_ITNS0</span></div>
<div class="line"><a id="l00069" name="l00069"></a><span class="lineno">   69</span>    <span class="comment">// For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state</span></div>
<div class="line"><a id="l00070" name="l00070"></a><span class="lineno">   70</span>    <span class="comment">// 0xffffffff [31:0]  ITNS         (0x00000000) For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security...</span></div>
<div class="line"><a id="l00071" name="l00071"></a><span class="lineno">   71</span>    io_rw_32 itns[2];</div>
<div class="line"><a id="l00072" name="l00072"></a><span class="lineno">   72</span> </div>
<div class="line"><a id="l00073" name="l00073"></a><span class="lineno">   73</span>    uint32_t _pad5[30];</div>
<div class="line"><a id="l00074" name="l00074"></a><span class="lineno">   74</span> </div>
<div class="line"><a id="l00075" name="l00075"></a><span class="lineno">   75</span>    <span class="comment">// (Description copied from array index 0 register M33_NVIC_IPR0 applies similarly to other array indexes)</span></div>
<div class="line"><a id="l00076" name="l00076"></a><span class="lineno">   76</span>    _REG_(M33_NVIC_IPR0_OFFSET) <span class="comment">// M33_NVIC_IPR0</span></div>
<div class="line"><a id="l00077" name="l00077"></a><span class="lineno">   77</span>    <span class="comment">// Sets or reads interrupt priorities</span></div>
<div class="line"><a id="l00078" name="l00078"></a><span class="lineno">   78</span>    <span class="comment">// 0xf0000000 [31:28] PRI_N3       (0x0) For register NVIC_IPRn, the priority of interrupt number...</span></div>
<div class="line"><a id="l00079" name="l00079"></a><span class="lineno">   79</span>    <span class="comment">// 0x00f00000 [23:20] PRI_N2       (0x0) For register NVIC_IPRn, the priority of interrupt number...</span></div>
<div class="line"><a id="l00080" name="l00080"></a><span class="lineno">   80</span>    <span class="comment">// 0x0000f000 [15:12] PRI_N1       (0x0) For register NVIC_IPRn, the priority of interrupt number...</span></div>
<div class="line"><a id="l00081" name="l00081"></a><span class="lineno">   81</span>    <span class="comment">// 0x000000f0 [7:4]   PRI_N0       (0x0) For register NVIC_IPRn, the priority of interrupt number...</span></div>
<div class="line"><a id="l00082" name="l00082"></a><span class="lineno">   82</span>    io_rw_32 ipr[16];</div>
<div class="line"><a id="l00083" name="l00083"></a><span class="lineno">   83</span> </div>
<div class="line"><a id="l00084" name="l00084"></a><span class="lineno">   84</span>} <a class="code hl_struct" href="structnvic__hw__t.html">nvic_hw_t</a>;</div>
<div class="line"><a id="l00085" name="l00085"></a><span class="lineno">   85</span> </div>
<div class="line"><a id="l00086" name="l00086"></a><span class="lineno">   86</span><span class="preprocessor">#define nvic_hw ((nvic_hw_t *)(PPB_BASE + M33_NVIC_ISER0_OFFSET))</span></div>
<div class="line"><a id="l00087" name="l00087"></a><span class="lineno">   87</span><span class="preprocessor">#define nvic_ns_hw ((nvic_hw_t *)(PPB_NONSEC_BASE + M33_NVIC_ISER0_OFFSET))</span></div>
<div class="line"><a id="l00088" name="l00088"></a><span class="lineno">   88</span><span class="keyword">static_assert</span>(<span class="keyword">sizeof</span> (<a class="code hl_struct" href="structnvic__hw__t.html">nvic_hw_t</a>) == 0x0340, <span class="stringliteral">&quot;&quot;</span>);</div>
<div class="line"><a id="l00089" name="l00089"></a><span class="lineno">   89</span> </div>
<div class="line"><a id="l00090" name="l00090"></a><span class="lineno">   90</span><span class="preprocessor">#endif </span><span class="comment">// _HARDWARE_STRUCTS_NVIC_H</span></div>
<div class="line"><a id="l00091" name="l00091"></a><span class="lineno">   91</span> </div>
<div class="ttc" id="aaddress__mapped_8h_html"><div class="ttname"><a href="address__mapped_8h.html">address_mapped.h</a></div></div>
<div class="ttc" id="astructnvic__hw__t_html"><div class="ttname"><a href="structnvic__hw__t.html">nvic_hw_t</a></div><div class="ttdef"><b>Definition:</b> nvic.h:26</div></div>
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